1. Field of the Invention
The present invention relates to the field of display, and in particular to a thin film transistor (TFT) substrate manufacturing method and TFT substrate.
2. The Related Arts
As display technology progresses, the liquid crystal display (LCD) shows the advantages of high display quality, low power-consumption, thinness, and wide applications, the LCD is widely used in various devices, such as, liquid crystal TV, mobile phones, PDA, digital camera, PC monitors or notebook PC screens, becomes the leading display technology.
The LCDs in current market are mostly backlit type LCDs, which comprises a LCD panel and a backlight module. The operation principle of the LCD panel is to disposed liquid crystal (LC) molecules between the two parallel glass substrates, which are disposed with a plurality of tiny wires vertically and horizontally in-between. By supplying electricity through the wires or not to control the LC molecules to change direction, the LC molecules can deflect the light from the backlight module to generate an image.
The LCD panel usually comprises a color filter (CF) substrate, a thin film transistor (TFT) substrate, a liquid crystal (LC) sandwiched between the CF substrate and the TFT substrate, and a sealant; wherein the TFT substrate is the main driving component in the LCD panel and is directly related to the development direction of high performance LCD.
As shown in FIGS. 1-3, the known TFT substrate manufacturing method comprises the following steps:
Step 1: as shown in FIG. 1, providing a base substrate 100, and forming, in subsequent order of, a buffer layer 200, an active layer 300, a gate insulation layer 400, a gate 500, and an interlayer dielectric layer 600;
Step 2: as shown in FIG. 2, performing etching simultaneously on the interlayer dielectric layer 600 and the gate insulation layer 400 to form vias on the interlayer dielectric layer 600 and the gate insulation layer 400 respectively corresponding to two ends of the active layer 300;
Step 3: as shown in FIG. 3, forming on the interlayer dielectric layer 600, in subsequent order of, a source 700 and a drain 800, a planarization layer 900, a common electrode 1000, a passivation layer 1100, and a pixel electrode 1200.
In Step 2 of the above TFT substrate manufacturing method, the process of performing simultaneous etching on the interlayer dielectric layer 600 and the gate insulation layer 400 is difficult to control because the interlayer dielectric layer 600 and the gate insulation layer 400 have a total thickness, which easily leads to non-penetrating vias or over-etching vias damaging the active layer 300, resulting in product defects. Therefore, it is imperative to devise an improve TFT substrate manufacturing method to address the above issue.